One widely used LDO regulator architecture comprises an error amplifier whose output node is connected to the gate of an output transistor, generally a PMOS power transistor, of the output stage. In order to decrease the capacitance on the output node of the error amplifier and thus decrease the charging or discharging time of the gate of the output transistor in the presence of high currents, a buffer circuit comprising a follower amplifier is inserted between the output node of the error amplifier and the gate of the output transistor.
However, the presence of such a buffer circuit adds an additional pole in the Bode diagram of the variations of the open-loop gain of the error amplifier as a function of the frequency of the signal. And the output pole of the regulator and this additional pole can then be situated at neighbouring frequencies, thus creating a complex conjugate pole which degrades the stability of the system.